Clock generator circuits are typically employed to generate one or more clock output signals based upon a clock input signal. One drawback of conventional clock generator circuits (e.g., clock generator integrated circuits or chips is their limited programmability.
For example, there is often limited programmability in terms of input/output signal types, input/output voltage levels, frequency range, output banking structure, and/or skew control (e.g., controlling the phase of a clock output signal relative to a clock input signal). Furthermore, if programming is available, the programming may have to be performed by pin strapping, which is difficult to implement, inflexible, and may require the utilization of a number of pins.
As an example of limited programmability, skew control may only be available on a per bank basis and may be limited to only very coarse skew adjustments. If the skew steps are too coarse, for example, expensive and time-consuming trace length adjustments may be necessary on the printed circuit board.
Another drawback of conventional clock generator circuits is their lack of support for joint test action group (JTAG) or other automated testing. Consequently, it can often be cumbersome, time-consuming, and expensive to test a circuit board having clock generator circuits and other components (e.g., microprocessors, field programmable gate arrays (FPGAs), or complex programmable logic devices (CPLDs)). As a result, there is a need for improved skew control and clock generation techniques.